--
-- VHDL Architecture Fietscomputer_lib.Fc_seq_deler_v2.v2
--
-- Created:
--          by - 10070052.Demi Staal (DTP7797)
--          at - 11:55:54 29-09-2011
--
-- using Mentor Graphics HDL Designer(TM) 2008.1b (Build 7)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
-- a/b
ENTITY Fc_seq_deler_v2 IS
  PORT (
    A     : IN     STD_LOGIC_VECTOR(63 DOWNTO 0);
    B     : IN     STD_LOGIC_VECTOR(63 DOWNTO 0);
    R     : OUT    STD_LOGIC_VECTOR(63 DOWNTO 0);
    clk   : IN     STD_LOGIC;
    rst   : IN     STD_LOGIC;
    start : IN     STD_LOGIC;
    ready : OUT    STD_LOGIC
    );
  END Fc_seq_deler_v2;
  
  --
  ARCHITECTURE v2 OF Fc_seq_deler_v2 IS
  
  Signal  Btemp : STD_LOGIC_VECTOR (63 DOWNTO 0);
  Signal  Atemp  : STD_LOGIC_VECTOR (63 DOWNTO 0);
  Signal  Result	: STD_LOGIC_VECTOR (63 DOWNTO 0) := (OTHERS => '0'); -- resultaat
  Signal  Shiften  : STD_LOGIC := '0'; -- shiften
  Signal  Running  : STD_LOGIC := '0';
  Signal  Ready_set: STD_LOGIC := '0';
  Signal  Timer  : Integer range 0 to 64 := 0; -- Teller 1
  
  BEGIN
    PROCESS(rst,clk)
      
      BEGIN
        IF rst = '1'THEN
          Atemp <= (OTHERS => '0');
          Btemp <= (OTHERS => '0');
          Result<= (OTHERS => '0');
          R<= (OTHERS => '0');
          Timer <= 0;
          ready <= '0';
          Running <= '0';
          ready_set <= '0';
          
        ELSIF RISING_EDGE(clk)THEN
          ready <= '0';
          IF start = '1' THEN
            IF running = '0' THEN
              if unsigned(B) /= 0 then
                Atemp <= A;
                Btemp <= B;
                result <= (OTHERS => '0');
                Shiften <= '0';
                Timer <= 1;
                ready <= '0';
                running <= '1';
                ready_set <= '0';
              end if;
            END IF;
          END IF;
            
            
            IF Btemp(62) = '1' THEN
              Shiften <= '1';
              
            END IF;
            
            IF Running = '1' THEN
              IF Shiften = '0' THEN
                Btemp(63 DOWNTO 1) <= Btemp(62 DOWNTO 0);
                Btemp(0) <= '0';
                Timer <= Timer+1;--telt de lengte van B
              END IF;
            END IF;
            
            IF Shiften = '1' THEN
              IF timer /= 0 THEN
                IF Atemp>=Btemp THEN
                  Atemp <= Atemp-Btemp;
                  Result(Timer-1) <= '1';
                END IF;
                
                Btemp(62 DOWNTO 0) <= Btemp(63 DOWNTO 1);
                Btemp(63) <= '0';
                Timer<=Timer-1;
              END IF;
              
              
              IF Timer = 0 THEN
                IF ready_set = '0' THEN
                  ready_set <= '1';
                  R <= result;
                  ready <= '1';
                  running <= '0';
                END IF;
              END IF;
              
              --              IF Timer = 1 THEN
              --                IF Shiften = '1' THEN
              --                  ready <= '1';
              --                END IF;
              --               END IF; 
              
              if unsigned(B) = 0 then
                ready <= '1';
              end if;            
            END IF;
            
          END IF;
 --       END IF;
      END PROCESS;
      
    END ARCHITECTURE v2;
    
    
